Non-volatile memory (NVM) circuits, such as electrically erasable programmable read-only memory (EEPROM) circuits have achieved widespread adoptions for code and data storage applications. An important aspect of NVM circuits is their cell size.
However, due to the demand for higher densities, there arises a need for NVM circuits with a reduced cell size as well as a reduction in programming voltage. Such NVM circuits should be able to be formed without increasing conventional processing steps thereby reducing the overall cost for the user.
It is, therefore, desirable to provide NVM memory cells formed from conventional processing steps with a reduced size thereby improving programming voltage and reducing the voltage stress.